Senior IC Layout Engineer

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Analog IC / RF IC Recruitment by day / Unity Game Developer by night

I am recruiting for a Senior IC Layout Design Engineer to join my client's design centre based near Delft, Netherlands.

The role also includes mentoring junior engineers and offshore layout contractors, helping to develop consistent layout methodologies and workflows across sites.

Key responsibilities:

• Top-level and block-level layout for analog and digital blocks
• Schematic driven layout and constraint-based design
• Chip level floorplanning, power distribution, shielding and device matching
• Layout verification including DRC, LVS, and ERC
• Chip-level integration and support for tape-out
• Training and guidance for junior and offshore layout engineers

Key requirements:

• 6-12 years' experience in layout design for analog and digital circuits
• Strong background in CMOS and BiCMOS, ideally including TSMC 180nm, 65nm, and 22nm nodes
• Proficient with Cadence Virtuoso and familiar with DRC/LVS/ERC tools (PVS or Calibre)
• Solid understanding of layout effects including parasitics, matching, EM, IR drop and crosstalk
• Familiarity with layout automation and scripting tools is a plus

My client offers a collaborative working environment with technically challenging projects, and the opportunity to influence layout practices company-wide.

Please note that this job requires 5 days on-site.

If you are a Senior IC Layout Design Engineer looking for a new opportunity in the Netherlands, feel free to get in touch for more details.

• Seniority level

Mid-Senior level

• Employment type

Full-time

• Industries

Semiconductor Manufacturing and Engineering Services

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